This application claims the priority benefit of Taiwan application serial no. 91115991, filed Jul. 18, 2002.
1. Field of Invention
The present invention relates to a method for fabricating a read only memory (ROM). More particularly, the present invention relates to a method for fabricating a nitride ROM.
2. Description of Related Art
The manufacture process for forming non-volatile read only memory (ROM) includes forming a trapping layer over the substrate. If the trapping layer consists of a stacked structure made of a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer, the ROM is called nitride ROM. The polysilicon gate is formed on the ONO layer as a word line. Afterwards, a source/drain region is formed in the substrate on both sides of the ONO layer, as a buried bit line.
As the memory device keeps minimizing, the length of the gate shrinks down. The buried bit line formed by ion implantation can easily have dopant diffusion during the thermal treatment, thus reducing the effective channel length of the device. To overcome the prior problems, shallow junctions (or ultra shallow junctions) together with pocket implant are used in developing devices of smaller sizes. However, the buried bit line consisting of shallow junction or ultra shallow junction usually has high resistance, so that the memory devices have difficulties in operation.
The invention provides a method for fabricating a nitride read only memory (NROM), which can decrease the resistance of the bit line.
The invention provides a method for fabricating a nitride read only memory (NROM), which can increase conductivity of the bit line.
The invention provides a method for fabricating a nitride read only memory (NROM), which can prevent the short channel effect resulting from dopant diffusion of the buried bit line during the thermal treatment.
As embodied and broadly described herein, the present invention provides a method for fabricating a nitride read only memory (NROM), comprising: forming a doped polysilicon layer over a substrate, forming a patterned mask layer on the doped polysilicon layer, defining the doped polysilicon layer to form a plurality of doped polysilicon lines and expose a portion of the substrate. Afterwards, a thermal process is performed to form an oxide layer on the exposed substrate and sidewalls of the doped polysilicon lines. During the thermal process, the dopants are driven into the substrate to form a source/drain region, thus obtaining a plurality of bit lines including the doped polysilicon lines and the source/drain region. Later on, the patterned mask layer is removed to expose a top surface of the bit lines. A self-aligned silicide process is performed to form a self-aligned silicide layer on the top surface of the bit lines. After removing the oxide layer, a silicon nitride stacked layer and a plurality of word lines are formed over the substrate.
Because the source/drain region formed under the doped polysilicon lines through the thermal treatment is used as the buried bit line, the present invention can greatly decrease the resistance of the bit line. The present invention can avoid short channel effect, since no dopant diffusion of the buried bit line occurs in the thermal process. In addition to the polysilicon lines and the source/drain region, the bit line further includes a self-aligned silicide layer on the top surface of the polysilicon lines, thus increasing conductivity of the bit line.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.